The present invention relates to a semiconductor device having a MOS transistor which is excellent in driving force and a method of fabricating the same.
The recent development of a highly integrated semiconductor device or so-called VLSI has required increasing miniaturization of MOS transistors as constituents of the VLSI. In the MOS transistors, an attempt has been made to reduce the dimensions of devices in different generations in accordance with scaling rules. In response to the reduced dimensions, substrate concentration has been increased to suppress a so-called short-channel effect and thereby improve the properties of the devices.
Among various dimensions of the device, however, the depth of an impurity layer as a source or drain is difficult to reduce. Under such circumstances, a structure for suppressing the short-channel effect has been proposed for a MOS transistor.
As a conventional embodiment, the structure of a MOS transistor shown in, e.g., xe2x80x9cHigh-Performance Devices for a 0.15 xcexcm CMOS technology (G. G. Shahidi et al, IEEE Electron Device Letters, vol. 14, no. 10, October 1993)xe2x80x9d (hereinafter simply referred to as the conventional MOS transistor) and a fabrication method therefor will be described with reference to FIG. 20.
As shown in FIG. 20, the conventional MOS transistor comprises: a pxe2x88x92-type well region 2 formed in a semiconductor substrate 1; a p-type channel region 3 formed in a surface portion of the semiconductor substrate 1; a gate electrode 5 formed on the channel region 3 with a gate insulating film 4 interposed therebetween, source/drain regions 9 composed of n+-type impurity layers formed in the respective regions of the surface portion of the semiconductor substrate 1 which are located on both sides of the gate electrode 5, extension regions 6 composed of n+-type impurity layers formed inwardly of the source/drain regions 9 in the surface portion of the semiconductor substrate 1, and p+-type pocket regions 7 formed in the surface portion of the semiconductor substrate 1 to cover the extension regions 6 and have an upper end portion extending to the gate insulating film 4.
The conventional MOS transistor comprises the p+-type pocket regions 7 formed to cover the n+-type extension regions 6. Since the pocket regions 7 inhibit depletion layers from extending from the n+-type extension regions 6 and the source/drain regions 9, the short-channel effect can be suppressed.
Even if the depth of the extension region 6 or of the source/drain regions 9 cannot be reduced in accordance with the scaling rules, the short-channel effect can be suppressed by increasing impurity concentration in the pocket regions 7.
However, the conventional MOS transistor has the following problems.
First Problem
If impurity concentration in the p+-type pocket regions is increased to further suppress the short-channel effect, impurity concentration in the extension regions is reduced as a result of cancellation, since the n+-type extension regions are covered with the pocket regions. This causes the problem that the resistance of the extension regions is increased and the driving force of the MOS transistor is thereby decreased. If impurity concentration in the p+-type pocket regions is increased, impurity concentration in the portions of the channel region adjacent the extension regions is also increased so that impurity scattering in a carrier flow is aggravated and the mobility of carriers is lowered. This further decreases the driving force of the MOS transistor. If impurity concentration in the portions of the channel region adjacent the extension regions is increased, a so-called reverse short-channel effect occurs to cause the problem that the threshold voltage of the transistor is largely dependent on the channel length of the transistor.
Second Problem
Sidewalls are formed by depositing, after the extension regions are formed by implanting n-type impurity ions and the pocket regions are formed by implanting p-type impurity ions, an insulating film over the entire surface of the semiconductor substrate at a low temperature of 600xc2x0 C. to 850xc2x0 C. for a period of several tens of minutes to several hours, and then performing anisotropic etching with respect to the insulating film. However, transient enhanced diffusion of the impurity is caused remarkably by point defects (voids and interstitial silicons) produced during the implantation of the impurity ions. This increases impurity concentration in the pocket regions so that the resistance of the extension regions increases and the mobility of carriers lowers. This decreases the driving force of the MOS transistor. Moreover, the interstitial silicons produced during the ion implantation for forming the extension regions and the pocket regions are diffused toward the gate insulating film during the low-concentration heat treatment (e.g., during the deposition of the insulating film as the sidewalls), so that a gradient is produced in the distribution. As a consequence, the impurity in the end portion of the channel region adjacent the gate electrode moves toward the substrate surface, which increases impurity concentration in the surface region of the end portion of the channel region adjacent the gate electrode. This causes the so-called reverse short-channel effect and varies the threshold voltage disadvantageously. The phenomenon is conspicuous when the pocket regions are formed by implanting boron ions.
Third Problem
In the method of fabricating the conventional MOS transistor, the p+-type pocket regions are amorphized by implanting indium ions therein such that the distribution of arsenic ions in the n+-type extension regions is sharpened.
However, the present inventors have newly found that a heat treatment performed after the amorphizing step causes point defects in the inner portions of the pocket regions adjacent the pn junction formed between the extension regions and the pocket regions (i.e., outside the extension regions). The point defects produced in the pocket regions cause a junction leakage current. If a VLSI having such a MOS transistor is incorporated into mobile communication equipment, there occurs the problem that the junction leakage current increases power consumption during standby.
In view of the foregoing, it is therefore an object of the present invention to increase the driving force of a MOS transistor.
To attain the object, a first semiconductor device according to the present invention comprises: a gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween; a channel region composed of a first-conductivity-type semiconductor layer formed in a region of a surface portion of the semiconductor substrate located below the gate electrode; source/drain regions composed of second-conductivity-type impurity layers formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode; second-conductivity-type extension regions formed between the channel region and respective upper portions of the source/drain regions in contact relation with the source/drain regions; and first-conductivity-type pocket regions formed between the channel region and respective lower portions of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.
Since the first semiconductor device comprises the first-conductivity-type pocket regions between the channel region and the respective lower portions of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film, impurity concentration in the extension regions does not decrease and impurity concentration in the portions of the channel region adjacent the extension regions does not increase even if impurity concentration in the pocket regions is increased to suppress the short-channel effect.
Since impurity concentration in the extension regions does not decrease, the resistance of the extension regions does not increase so that a decrease in the driving force of the MOS transistor is suppressed. Moreover, since impurity concentration in the portions of the channel region adjacent the extension regions does not increase, the lowering of the mobility of carriers due to impurity scattering in a carrier flow is prevented so that a decrease in the driving force of the MOS transistor is prevented.
Accordingly, the first semiconductor device prevents a decrease in the driving force of the MOS transistor, while suppressing the short-channel effect.
Preferably, the first semiconductor device further comprises: first-conductivity-type lightly doped channel regions formed in both side portions of the channel region in contact relation with the extension regions, each of the lightly doped channel regions containing an activated impurity at a concentration lower than in a center portion of the channel region.
In the arrangement, the lightly doped channel regions containing the activated impurity at a concentration lower than in the center portion of the channel region are provided on both side portions of the channel region in contact relation to the extension regions. As a consequence, the concentration of the activated impurity in the upper portions of the channel region is lower in both side portions thereof adjacent the source/drain regions and higher in the middle portion thereof. In other words, the concentration of the activated impurity in the portions of the channel region in contact with the extension regions is lower.
Accordingly, the resistance of the extension regions is further lowered so that a decrease in the driving force of the MOS transistor is prevented more positively.
A second semiconductor device according to the present invention comprises: a gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween; a channel region composed of a first-conductivity-type semiconductor layer doped with indium ions and formed in a region of a surface portion of the semiconductor substrate located below the gate electrode; source/drain regions composed of second-conductivity-type impurity layers formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode; second-conductivity-type extension regions formed between the channel region and respective upper portions of the source/drain regions in contact relation with the source/drain regions; and first-conductivity-type lightly doped channel regions formed in both side portions of the channel region in contact relation with the extension regions, each of the lightly doped channel regions containing an activated impurity at a concentration lower than in a center portion of the channel region.
In the second semiconductor device, the lightly-doped channel regions containing the activated impurity at a concentration lower than in the center portion of the channel region are provided in both side portions of the channel region in contact relation with the extension regions. As a consequence, the concentration of the activated impurity in the upper portions of the channel region is lower in both side portions thereof adjacent the source/drain regions and higher in the middle portion thereof. In other words, the concentration of the activated impurity in the portions of the channel region in contact with the extension regions is lower. This lowers the resistance of the extension regions and prevents a decrease in the driving force of the MOS transistor.
A first method of fabricating a semiconductor device according to the present invention comprises the steps of: ion implanting a first-conductivity-type impurity into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting a second-conductivity-type impurity into the semiconductor layer by using the gate electrode as a mask to form first second-conductivity-type impurity layers in upper portions of the semiconductor layer; implanting indium ions into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type impurity layers in lower portions of the semiconductor layer; performing a short-time heat treatment with respect to the semiconductor substrate at a temperature of about 950xc2x0 C. to 1050xc2x0 C.; forming sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the first-conductivity-type impurity layers by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the first-conductivity-type impurity layers located on both sides of the gate electrode, form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers, and form first-conductivity-type pocket regions inwardly of respective lower portions of the source/drain regions in the respective first-conductivity-type impurity layers.
In accordance with the first method of fabricating the semiconductor device, the first-conductivity-type impurity layers as the pocket regions are formed by implanting indium ions having an atomic mass larger than that of boron ions. As a consequence, the distribution of impurity concentration in the pocket regions has a peak in a shallow position and the extent to which the pocket regions expand is limited. Since the diffusion coefficient of indium ions is lower than that of boron ions, the expansion of the pocket regions due to thermal diffusion is suppressed.
Like boron ions, indium ions have the possibility of undergoing transient enhanced diffusion caused by point defects produced during ion implantation. However, the first method of fabricating the semiconductor device allows suppression of transient enhanced diffusion caused by the point defects since it forms the first-conductivity-type impurity layers as the pocket regions by implanting indium ions and then performs the short-time heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C.
Therefore, the first method of fabricating the semiconductor device ensures the fabrication of the first semiconductor device having the pocket regions disposed in spaced relation to the gate insulating film.
In the first method of fabricating a semiconductor device, a dose of the indium ions in the step of forming the first-conductivity-type impurity layers is preferably 5xc3x971013 cmxe2x88x922 or less.
In the arrangement, the silicon crystal is not amorphized in the first-conductivity-type impurity layers as the pocket regions and EOR point defects such as dislocation loops are not produced, so that the occurrence of a junction leakage current is prevented.
A second method of fabricating a semiconductor device according to the present invention comprises the steps of: ion implanting a first-conductivity-type impurity into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting an atom belonging to the Group IV into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type amorphous layers in upper portions of the semiconductor layer; ion implanting a second-conductivity-type impurity into the amorphous layers by using the gate electrode as a mask to form first second-conductivity-type impurity layers in the respective amorphous layers; implanting indium ions into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type impurity layers in lower portions of the semiconductor layer; performing a short-time heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C. with respect to the semiconductor substrate; forming sidewalls on side surfaces of the gate electrode; ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the first-conductivity-type impurity layers by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the first-conductivity-type impurity layers located on both sides of the gate electrode, form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers, and form first-conductivity-type pocket regions inwardly of respective lower portions of the source/drain regions in the respective first-conductivity-type impurity layers.
In accordance with the second method of fabricating the semiconductor device, the first-conductivity-type impurity layers as the pocket regions are formed by implanting indium ions having an atomic mass larger than that of boron ions and a diffusion coefficient lower than that of boron ions, similarly to the first method of fabricating the semiconductor device. As a consequence, the distribution of impurity concentration in the pocket regions has a peak in a shallow position and the extent to which the pocket regions expand is limited. In addition, the expansion of the pocket regions by thermal diffusion is suppressed. Therefore, the second method of fabricating the semiconductor device ensures the fabrication of the first semiconductor device having the pocket regions disposed in spaced relation to the gate insulating film.
Since the second method of fabricating the semiconductor device has formed the amorphous layers in the upper portions of the first-conductivity-type semiconductor layer and then formed the first second-conductivity-type impurity layers as the extension regions by ion implanting the second-conductivity-type impurity, the distribution of impurity concentration in the first second-conductivity-type impurity layers becomes particularly sharp. This lowers the resistance of the extension regions and thereby increase the driving force of the MOS transistor.
In the second method of fabricating a semiconductor device, a dose of the indium ions in the step of forming the first-conductivity-type impurity layers is preferably 5xc3x971013 cmxe2x88x922 or less.
In the arrangement, the silicon crystal is not amorphized in the first-conductivity-type impurity layers as the pocket regions and the EOR point defects such as the dislocation loops are not produced, so that the occurrence of the junction leakage current is prevented.
A third method of fabricating a semiconductor device according to the present invention comprises the steps of: implanting indium ions into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting a second-conductivity-type impurity into the semiconductor layer by using the gate electrode as a mask to form first second-conductivity-type impurity layers in upper portions of the semiconductor layer; depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600xc2x0 C. to 850xc2x0 C. to form first-conductivity-type lightly doped channel regions inwardly of the respective first second-conductivity-type impurity layers and in upper portions of the semiconductor layer, each of the lightly doped channel regions containing the impurity at a concentration lower than in the semiconductor layer; performing anisotropic etching with respect to the insulating film to form sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the semiconductor layer by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the semiconductor layer located on both sides of the gate electrode and form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers.
The third method of fabricating the semiconductor device comprises the steps of: implanting indium ions to form the first-conductivity-type semiconductor layer as the channel region; and ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions and performing the low-temperature long-time heat treatment at a temperature of about 600xc2x0 C. to 850xc2x0 C. in depositing the insulating film. Although interstitial silicon atoms generated during the formation of the first second-conductivity-type impurity layers as the extension regions by ion implantation are caused to move toward the gate insulating film by the low-temperature long-time heat treatment, they are bonded to indium ions present in the portions of the first-conductivity-type semiconductor layer underlying both side portions of the gate insulating film to inactivate the indium ions. As a consequence, the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer are formed in the portions of the first-conductivity-type semiconductor layer as the channel region which underlie the both side portions of the gate insulating film, i.e., inwardly of the respective first second-conductivity-type impurity layers in the first-conductivity-type semiconductor layer.
Therefore, the third method of fabricating the semiconductor device ensures the fabrication of the second semiconductor device having the lightly doped channel regions each containing the activated impurity at a concentration lower than in the center portion of the channel region in the both side portions of the channel region.
A fourth method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a first-conductivity-type semiconductor layer as a channel region by implanting indium ions into a surface portion of a semiconductor substrate; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting an atom belonging to the Group IV by using the gate electrode as a mask to form first-conductivity-type amorphous layers in upper portions of the semiconductor layer; ion implanting a second-conductivity-type impurity into the amorphous layers by using the gate electrode as a mask to form first second-conductivity-type impurity layers; depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600xc2x0 C. to 850xc2x0 C. to form first-conductivity-type lightly doped channel regions inwardly of the respective first second-conductivity-type impurity layers and in upper portions of the semiconductor layer, each of the lightly doped channel regions containing the impurity at a concentration lower than in the semiconductor layer; performing anisotropic etching with respect to the insulating film to form sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the semiconductor layer by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the semiconductor layer located on both sides of the gate electrode and form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers.
The fourth method of fabricating the semiconductor device comprises the steps of: implanting indium ions to form the first-conductivity-type semiconductor layer as the channel region; and ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions and performing the low-temperature long-time heat treatment at a temperature of about 600xc2x0 C. to 850xc2x0 C. in depositing the insulating film, similarly to the third method of fabricating the semiconductor device. In moving toward the gate insulating film, the interstitial silicon atoms are bonded to indium ions present in the portions of the first-conductivity-type semiconductor layer underlying both side portions of the gate insulating film to inactivate the indium ions. As a consequence, the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer are formed inwardly of the first second-conductivity-type impurity layers in the first-conductivity-type semiconductor layer.
Since the fourth method of fabricating the semiconductor device comprises the step of forming the amorphous layers in the upper portions of the first-conductivity-type semiconductor layer by ion implanting an atom belonging to the Group IV prior to the step of ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions, the number of interstitial silicon atoms generated in the upper portions of the first-conductivity-type semiconductor layer is increased, so that the number of indium ions bonded to the interstitial silicon atoms and thereby inactivated is increased. This allows efficient formation of the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer.
A fifth method of fabricating a semiconductor device according to the present invention comprises the steps of: implanting indium ions into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting a second-conductivity-type impurity into the semiconductor layer by using the gate electrode as a mask to form first second-conductivity-type impurity layers in upper portions of the semiconductor layer; performing a long-time first heat treatment with respect to the semiconductor substrate at a temperature of about 600xc2x0 C. to 850xc2x0 C. to form first-conductivity-type lightly doped channel regions inwardly of the respective first second-conductivity-type impurity layers and in upper portions of the semiconductor layer, each of the lightly doped channel regions containing the impurity at a concentration lower than in the semiconductor layer; implanting indium ions into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type impurity layers in lower portions of the semiconductor layer; performing a short-time second heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C. with respect to the semiconductor substrate; forming sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the first-conductivity-type impurity layers by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the first-conductivity-type impurity layers located on both sides of the gate electrode, form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers, and form first-conductivity-type pocket regions inwardly of respective lower portions of the source/drain regions in the respective first-conductivity-type impurity layers.
The fifth method of fabricating the semiconductor device comprises the steps of: implanting indium ions to form the first-conductivity-type semiconductor layer as the channel region; and ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions and then performing the low-temperature long-time heat treatment at a temperature of about 600xc2x0 C. to 850xc2x0 C. In moving toward the gate insulating film, the interstitial silicon atoms are bonded to indium ions present in the lower portions of the first-conductivity-type semiconductor layer located on both sides of the gate insulating film to inactivate the indium ions, similarly to the third method of fabricating the semiconductor device. As a consequence, the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer are formed inwardly of the respective first second-conductivity-type impurity layers in the first-conductivity-type semiconductor layer. This ensures the fabrication of the semiconductor device having the lightly doped channel regions each containing the activated impurity at a concentration lower than in the center portion of the channel region in both side portions of the channel region.
Since the fourth method of fabricating the semiconductor device further comprises the step of implanting indium ions to form the first-conductivity-type impurity layers as the pocket regions and then performing the high-temperature short-time heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C., the distribution of impurity concentration in the pocket regions has a peak in a shallower position and the extent to which the pocket regions expand is limited, while the expansion of the pocket regions by thermal diffusion is suppressed, similarly to the first method of fabricating the semiconductor device. This ensures the fabrication of the semiconductor device having the pocket regions disposed in spaced relation to the gate insulating film.
A sixth method of fabricating a semiconductor device comprises the steps of: ion implanting a first-conductivity-type impurity into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting an atom belonging to the Group IV into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type amorphous layers in upper regions of the semiconductor layer; ion implanting a second-conductivity-type impurity into the amorphous layers by using the gate electrode as a mask to form first second-conductivity-type impurity layers in the respective amorphous layers; depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600xc2x0 C. to 850xc2x0 C. to form first-conductivity-type lightly doped channel regions inwardly of the first second-conductivity-type impurity layers and in upper portions of the semiconductor layer, each of the lightly doped channel regions containing the impurity at a concentration lower than in the semiconductor layer; performing anisotropic etching with respect to the insulating film to form sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the semiconductor layer by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective lower portions of the first second-conductivity-type impurity layers and the semiconductor layer located on both sides of the gate electrode and form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers; and after removing the sidewalls, implanting indium ions into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type pocket regions inwardly of respective lower portions of the source/drain regions and in lower portions of the semiconductor layer.
Since the sixth method of fabricating the semiconductor device comprises the steps of: implanting indium ions to form the first-conductivity-type semiconductor layer as the channel region; implanting ions of an atom belonging to the Group IV to form the amorphous regions in the upper portions of the first-conductivity-type semiconductor layer; and ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions and then performing the low-temperature long-time heat treatment at a temperature of about 600xc2x0 C. to 850xc2x0 C., the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer can be formed efficiently inwardly of the respective first second-conductivity-type impurity layers in the first-conductivity-type semiconductor layer, similarly to the fourth method of fabricating the semiconductor device.
Since the sixth method of fabricating the semiconductor device further comprises the step of performing the high-temperature short-time heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C. after implanting indium ions to form the first-conductivity-type impurity layers as the pocket regions, the distribution of impurity concentration in the pocket regions has a peak in a shallow position and the extent to which the pocket regions expand is limited, while the expansion of the pocket regions by thermal diffusion is suppressed, similarly to the first method of fabricating the semiconductor device. This ensures the fabrication of the semiconductor device having the pocket regions disposed in spaced relation to the gate insulating film.
Since the sixth method of fabricating the semiconductor device further comprises the step of forming the amorphous layers in the upper portions of the first-conductivity-type semiconductor layer and then ion implanting the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension region, it sharpens the distribution of impurity concentration in the first second-conductivity-type impurity layers, similarly to the second method of fabricating the semiconductor device, so that the resistance of the extension regions is reduced.
A seventh method of fabricating a semiconductor device according to the present invention comprises the steps of: implanting indium ions into a surface portion of a semiconductor substrate to form a first-conductivity-type semiconductor layer as a channel region; forming a gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; ion implanting an atom belonging to the Group IV by using the gate electrode as a mask to form Group-IV-atom-ion implanted layers in upper portions of the semiconductor layer; performing a long-time first heat treatment with respect to the semiconductor substrate at a temperature of about 600xc2x0 C. to 850xc2x0 C. to form first-conductivity-type lightly doped impurity layers into respective upper portions of the Group-IV-atom-ion implanted layers and the semiconductor layer, each of the lightly doped impurity layers containing the activated impurity at a concentration lower than in the semiconductor layer; implanting indium ions into the semiconductor layer by using the gate electrode as a mask to form first-conductivity-type impurity layers in lower portions of the semiconductor layer; ion implanting a second-conductivity-type impurity into the semiconductor layer by using the gate electrode as a mask to form first second-conductivity-type impurity layers in upper portions of the semiconductor layer and form lightly doped channel regions composed of the first-conductivity-type lightly doped impurity layers inwardly of the respective first second-conductivity-type impurity layers; performing a short-time second heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C. with respect to the semiconductor substrate; forming sidewalls on side surfaces of the gate electrode; and ion implanting a second-conductivity-type impurity into the first second-conductivity-type impurity layers and into the first-conductivity-type impurity layers by using the gate electrode and the sidewalls as a mask to form source/drain regions each composed of a second second-conductivity-type impurity layer in respective regions of the first second-conductivity-type impurity layers and the first-conductivity-type impurity layers located on both sides of the gate electrode, form second-conductivity-type extension regions inwardly of respective upper portions of the source/drain regions in the respective first second-conductivity-type impurity layers, and form first-conductivity-type pocket regions inwardly of respective lower portions of the source/drain regions in the respective first-conductivity-type impurity layers.
Since the seventh method of fabricating the semiconductor device comprises the steps of: implanting indium ions to form the first-conductivity-type semiconductor layer as the channel region; ion implanting an atom belonging to the Group IV to form the Group-IV-atom-ion implanted layers; and performing the long-time first heat treatment at a temperature of about 600xc2x0 C. to 850xc2x0 C. with respect to the semiconductor substrate, the lightly doped channel regions each containing the activated impurity at a concentration lower than in the first-conductivity-type semiconductor layer can be formed efficiently inwardly of the respective first second-conductivity-type impurity layers in the first-conductivity-type semiconductor layer.
Since the seventh method of fabricating the semiconductor device further comprises the step of performing the high-temperature short-time heat treatment at a temperature of about 950xc2x0 C. to 1050xc2x0 C. after implanting indium ions to form the first-conductivity-type impurity layers as the pocket regions, the distribution of impurity concentration in the pocket regions has a peak in a shallow position and the extent to which the pocket regions expand is limited, while the expansion of the pocket regions by thermal diffusion is suppressed. This ensures the fabrication of the semiconductor device having the pocket regions disposed in spaced relation to the gate insulating film.
Since the seventh method of fabricating the semiconductor device implants indium ions to form the first-conductivity-type impurity layers as the pocket regions and then ion implants the second-conductivity-type impurity to form the first second-conductivity-type impurity layers as the extension regions, the phenomenon of the channeling of the second-conductivity-type impurity ions in the first second-conductivity-type impurity layers is suppressed. This sharpens the distribution of impurity concentration in the extension regions composed of the first second-conductivity-type impurity layers, so that the parasitic resistance of the extension regions is reduced and the short-channel effect is suppressed.